Semiconductor device and method of production of same

ABSTRACT

A semiconductor device, enabling reliable electrical connection of a main electrode pad with an interconnection pattern without separate provision of a via use electrode pad in addition to the existing main electrode pad, provided with a silicon substrate (semiconductor substrate), an electronic element formation layer formed on one surface of that silicon substrate, an electrode pad having an extension and electrically connected to the electronic element formation layer, a through hole passing through the electrode pad and the silicon substrate, an SiO 2  film (insulating film), a via hole provided in the SiO 2  film on the extension of the electrode pad, and an interconnection pattern electrically leading out the electrode pad to the other surface of the silicon substrate through the through hole and via hole, said through hole having a diameter larger at a portion passing through the electrode pad than a portion passing through the semiconductor substrate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and amethod of production of the same, more particularly relates to asemiconductor device in which the insulation is secured between anelectrode pad and a semiconductor substrate at the side walls of athrough hole passing through the electrode pad and the semiconductorsubstrate, and a method of production of the same.

[0003] 2. Description of the Related Art

[0004] In the past, a semiconductor device to be mounted on amotherboard has been comprised of a semiconductor chip mounted on awiring board called an “interposer”. This interposer has been considerednecessary for aligning the positions of the electrode terminals of thesemiconductor chip and motherboard.

[0005] If an interposer is used, however, the thickness of thesemiconductor device increases by the amount of that thickness, so it ispreferable not to use such an interposer as much as possible so as tomeet with the recent demands for reducing the size of electronicequipment.

[0006] Therefore, in recent years, effort has been underway to develop asemiconductor device not requiring an interposer. A sectional view ofsuch a semiconductor device of the related art is shown in FIG. 9A.

[0007] The semiconductor device 101 of the related art is mainlycomprised of a silicon substrate 102 and does not have an interposer.One surface 102 a of the silicon substrate 102 has formed on it anelectronic element formation layer 103 including a transistor or otherelectronic element. This is electrically connected with a via holeelectrode pad 110. An insulating film 104 prevents electrical connectionof the via hole electrode pad 110 or main electrode pad 105 with thesilicon substrate 102.

[0008] The semiconductor element formation layer 103 and via holeelectrode pad 110 have stacked over them an SiO₂ film 106 and aninterconnection pattern 107. The SiO₂ film 106 has a via hole 106 aopened in it. The interconnection pattern 107 and via hole electrode pad110 are electrically connected through this opening.

[0009] The via hole electrode pad 110 is provided integrally with themain electrode pad 105. Further, the main electrode pad 105 and thesilicon substrate 102 under it have a through hole 111 opened in them.

[0010] The through hole 111 is a characterizing feature of this type ofsemiconductor device and is provided to lead out the interconnectionpattern 107 to the other surface 102 b of the silicon substrate 102. Theinterconnection pattern 107 led out to the other surface 102 b isprovided with solder bumps 108 functioning as external connectionterminals to be aligned in position with the terminals of themotherboard (not shown).

[0011]FIG. 9C is a plan view of the semiconductor device 101 seen fromthe direction of the arrow A of FIG. 9A. For convenience in explanation,the interconnection pattern 107 is omitted.

[0012] The via hole 106 a is a wide diameter circle at the bottom ofwhich the via hole electrode pad 110 is exposed.

[0013] The semiconductor device 101 is fabricated by building in astructure new to the existing semiconductor device (LSI etc.) 109 shownin section in FIG. 11. As will be explained using FIG. 11, the mainelectrode pad 105 is provided at the existing semiconductor device 109as well. This is the location where originally bonding wires, studbumps, etc. are bonded, signals are input and output, and power issupplied.

[0014] On the other hand, the via hole electrode pad 110 (FIG. 9C) isone of the new structures and is not provided in existing semiconductordevices 109. The via hole electrode pad 110 is newly provided toincrease the contact area with the interconnection pattern 107 (FIG. 9A)by providing a wide-diameter via hole 106 a above it and to preventpeeling with the interconnection pattern 107 due to stress and poorelectrical contact arising due to the same.

[0015] In this way, in the semiconductor devices of the related art, inaddition to the originally present main pad 105, a via hole pad 110 isnewly provided as a part for electrical connection with theinterconnection pattern 107 and, to ensure reliable electricalconnection, a wide-diameter circular via hole 106 a is opened above thevia hole electrode pad 110.

[0016] Referring now to FIG. 9B, the through hole 111 is defined by anopening 102 c of the silicon substrate 102, an opening 104 a of theinsulating film 104 and an opening 105 a of the main electrode pad 105.Therefore, at the side walls of the through hole 111, the siliconsubstrate 102 and the main electrode pad 105 are insulated from eachother by being distant from each other by a height D2 along the sidewalls.

[0017] However, the height D2 is relatively small, so it is difficult tosecure sufficient insulation between the silicon substrate 102 and themain electrode pad 105 at the side walls of the through hole 111.

[0018] Moreover, there is also a problem in the process of producing thesemiconductor device 101. This will be describe by referring to FIGS.10A and 10B, which are sectional views of the semiconductor device 101of the related art.

[0019] First, a silicon substrate in the state shown in FIG. 10A isprepared. In this state, the insulating film 104, the main electrode pad105 and the electronic element forming layer 103 are formed on thesilicon substrate 102.

[0020] Next, as shown in FIG. 10B, a laser beam is fired from the sideof the main electrode pad 105 and the portion struck by the laser beamvaporizes, whereby the through hole 111 is formed.

[0021] In this method, however, the materials of the main electrode pad105 and/or the silicon substrate 102 are vaporized by the laser beam andthe vaporized conducting materials (silicon, aluminum, copper, etc.)deposit on the opening 104 a of the insulating film 104, so there is thedanger of electrically connecting the silicon substrate 102 and the mainelectrode pad 105.

SUMMARY OF THE INVENTION

[0022] An object of the present invention is to provide a semiconductordevice having a through hole passing through an electrode pad and asemiconductor substrate, in which sufficient insulation between theelectrode pad and the semiconductor substrate at the side walls of thethrough hole is secured.

[0023] Another object of the present invention is to provide a method ofproducing a semiconductor device including forming a through holepassing through an electrode pad and a semiconductor substrate, in whichthe danger of electrically connecting the electrode pad and the siliconsubstrate is reduced.

[0024] To achieve the object, according to a first aspect of the presentinvention, there is provided a semiconductor device comprised of asemiconductor substrate; an electronic element formed on one surface ofthe semiconductor substrate; an electrode pad having an extension,formed on that one surface and electrically connected with the element;a through hole passing through the electrode pad and the semiconductorsubstrate; an insulating film formed on at least the other surface ofthe semiconductor substrate, an inner wall of the through hole, and theelectrode pad including the extension; a via hole provided in theinsulating film on the extension of the electrode pad; and aninterconnection pattern electrically leading out the electrode pad tothe other surface of the semiconductor substrate through the throughhole and the via hole, said through hole having a diameter larger at aportion passing through the electrode pad than a portion passing throughthe semiconductor substrate.

[0025] In one embodiment, the interconnection pattern electrically leadsout the electrode pad to the one surface of the semiconductor substrateas well. It is possible to stack a plurality of these semiconductordevices together and electrically connect interconnection patterns offacing surfaces of each bottom semiconductor device and topsemiconductor device through external connection terminals.

[0026] In one embodiment, the through holes are filled by a conductorelectrically connected with the interconnection patterns. It is possibleto stack a plurality of these semiconductor devices and electricallyconnect conductors filled in corresponding through holes of each bottomsemiconductor device and top semiconductor device through externalconnection terminals.

[0027] According to a second aspect of the invention, there is provideda method of production of a semiconductor device comprising the steps offorming an electronic element on one surface of a semiconductorsubstrate; forming an electrode pad electrically connected with theelement on the one surface of the semiconductor substrate; forming afirst opening in the electrode pad by patterning; forming a secondopening in the semiconductor substrate including the electronic elementby firing through the first opening a laser beam of a smaller diameterthan the diameter of the first opening, thereby defining a through holeby the first opening and the second opening; forming an insulating filmon at least the other surface of the semiconductor substrate, an innerwall of the through hole, and the electrode pad including the extension;forming a via hole exposing part of the extension of the electrode padby patterning the insulating film; forming a conductive film on theinsulating film and in the via hole; and forming an interconnectionpattern electrically leading the electrode pad to the other surface ofthe semiconductor substrate through the through hole and the via hole bypatterning the conductive film.

[0028] Preferably, the step of forming the first opening and the step offorming the second opening include between them a step of polishing theother surface of the semiconductor substrate to reduce the thickness ofthe semiconductor substrate.

[0029] Preferably, the step of forming the via hole is performed byopening the insulating film by a laser beam.

[0030] In one embodiment, by the step of forming the interconnectionpattern, the interconnection pattern is formed so that the electrode padis electrically led out to the one surface of the semiconductorsubstrate as well. It is possible to provide the steps of preparing aplurality of such semiconductor devices and stacking the semiconductordevices in a plurality of layers by electrically connecting theinterconnection patterns of the semiconductor device through externalconnection terminals.

[0031] In one embodiment, the method includes a step of filling thethrough holes by a conductor electrically connected to the conductivefilm after the step of forming the conductive film. It is possible toprovide the steps of preparing a plurality of such semiconductor devicesand stacking the semiconductor devices in a plurality of layers byelectrically connecting the conductors exposed from openings ofcorresponding through holes of the plurality of semiconductor devicesthrough external connection terminals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] These and other objects and features of the present inventionwill become clearer from the following description of the preferredembodiments given with reference to the attached drawings, wherein:

[0033]FIGS. 1A, 1B, and 1C are sectional views of a semiconductor deviceaccording to a preferred embodiment of the present invention, whereinFIG. 1B is an enlarged view of a portion in a circle 1B in FIG. 1A, andFIG. 1C is an enlarged view of a portion in a circle 1C in FIG. 1B;

[0034]FIG. 2 is a plan view of a semiconductor device according to anembodiment of the present invention shown in FIG. 1A seen from the Aside of FIG. 1A;

[0035]FIG. 3 is a sectional view of a semiconductor module obtained bystacking a plurality of semiconductor devices according to an embodimentof the present invention to obtain a three-dimensional mountingstructure;

[0036]FIGS. 4A to 4Q are sectional views of steps of producing asemiconductor device according to an embodiment of the presentinvention, wherein FIG. 4P shows the portion in the circle 4P in FIG. 4Oenlarged;

[0037]FIG. 5 is a sectional view of the state of preparing a pluralityof semiconductor devices for stacking according to an embodiment of thepresent invention;

[0038]FIG. 6 is a sectional view of a step of forming a protective filmperformed between the step of FIG. 4K and the step of FIG. 4L accordingto an embodiment of the present invention;

[0039]FIG. 7 is an enlarged sectional view of the case of filling athrough hole with a conductor according to an embodiment of the presentinvention;

[0040]FIG. 8 is a sectional view of a semiconductor module obtained bystacking a plurality of semiconductor devices with through holes filledby a conductor as shown in FIG. 7 to form a three-dimensional mountingstructure;

[0041]FIG. 9A and FIG. 9C are a sectional view and a plan view of asemiconductor device of the related art, while FIG. 9B is an enlargedsectional view of the portion in the circle 9B in FIG. 9A;

[0042]FIG. 10A and FIG. 10B are sectional views of the steps ofproducing a semiconductor device of the related art; and

[0043]FIG. 11 is a sectional view of a conventional existingsemiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] Preferred embodiments of the present invention will be describedin detail below while referring to the attached figures.

[0045] A semiconductor device according to the present invention isprovided with a semiconductor substrate and an electronic element formedon one surface of the semiconductor substrate. An electrode padelectrically connected with this element is formed on that surface ofthe semiconductor substrate. The electrode pad and the semiconductorsubstrate have a through hole passing through them. An insulating filmis formed on the inner wall of that through hole. This insulating filmis further formed on the other surface of the semiconductor substrateand on the electrode pad.

[0046] In the insulating film, the portion formed on the extension ofthe electrode pad is provided with a via hole. An interconnectionpattern electrically leading the electrode pad to the other surface ofthe semiconductor substrate through the via hole and the through hole isprovided in the semiconductor device.

[0047] In particular, in the present invention, the diameter of thethrough hole is preferably made larger at the portion passing throughthe electrode pad (hereinafter called the “first opening”) than theportion passing through the semiconductor substrate (hereinafter calledthe “second opening”).

[0048] According to this structure, compared with the structure of therelated art in which the diameter of the through hole is constantregardless of the location, it is possible to extend the distancebetween the near open ends of the first opening and second opening, sothe insulation between the electrode pad and the semiconductor substrateat the side walls of the through hole is sufficiently secured.

[0049] Further, the interconnection pattern may electrically lead outthe electrode pad to one surface of the semiconductor substrate.

[0050] In this case, by preparing a plurality of such semiconductordevices in a vertical direction and electrically connecting theinterconnection patterns of the facing surfaces of each bottomsemiconductor device and top semiconductor device through externalconnection terminals, a three-dimensional mounting structure isobtained. Since the planar size of each semiconductor device is smallerthan in the past, this three-dimensional mounting structure keeps downthe spread in the lateral direction compared with the past.

[0051] When stacking devices in this way, it is possible to fill thethrough holes by a conductor electrically connected with theinterconnection patterns. In this case, the conductors at the locationsexposed from the through holes perform the function of theinterconnection patterns, so there is no longer a need to form thoseinterconnection patterns and the top and bottom semiconductor devicescan be easily stacked.

[0052] On the other hand, a method of production of a semiconductordevice according to the present invention comprises the steps of:

[0053] (a) forming an electronic element on one surface of asemiconductor substrate;

[0054] (b) forming an electrode pad having an extension and electricallyconnected with the element on the one surface of the semiconductorsubstrate;

[0055] (c) forming a first opening in the electrode pad by patterning;

[0056] (d) forming a second opening in the semiconductor substrateincluding the electronic element by firing through the first opening alaser beam of a smaller diameter than the diameter of the first opening,thereby defining a through hole by the first opening and the secondopening;

[0057] (e) forming an insulating film on at least the other surface ofthe semiconductor substrate, an inner wall of the through hole, and theelectrode pad including the extension;

[0058] (f) forming a via hole exposing part of the extension of theelectrode pad by patterning the insulating film;

[0059] (g) forming a conductive film on the insulating film and in thevia hole; and

[0060] (h) forming an interconnection pattern electrically leading theelectrode pad to the other surface of the semiconductor substratethrough the through hole and the via hole by patterning the conductivefilm.

[0061] According to steps (c) and (d) among these steps, since a laserbeam of a smaller diameter than the diameter of the first opening isfired through the first opening after forming it, the laser beam can beprevented from contacting the first opening and vaporizing the materialof the electrode pad, so the danger of the semiconductor substrate andthe electrode pad ending up becoming electrically connected by vaporizedmaterial is lessened.

[0062] In addition, according to the above steps, a structure isobtained in which the diameter of the first opening is larger than thediameter of the second opening. As already explained, this structure hasthe advantage that insulation between the electrode pad andsemiconductor substrate at the side walls of the through hole issufficiently secured.

[0063] Further, steps (c) and (d) may include between them a step ofpolishing the other surface of the semiconductor substrate to reduce thethickness of the semiconductor substrate.

[0064] According to this, since the semiconductor substrate is reducedin thickness before forming the second opening, it is possible to formthe second opening by firing a laser beam for a short time and the heatdamage to the semiconductor substrate arising due to the firing of thelaser beam is reduced. Further, since the depth of working by the laserbeam becomes shallow, the amount of vaporization of the material by thelaser beam is reduced and the amount of the material vaporizing anddepositing in the through hole is reduced. Due to this, it is possibleto cleanly form the through hole.

[0065] Further, step (f) (step of forming the via hole in the insulatingfilm) may be performed by opening the insulating film by a laser beam.

[0066]FIGS. 1A, 1B, and 1C are sectional views of a semiconductor deviceaccording to a preferred embodiment of the present invention. FIG. 1B isan enlarged view of the area in the circle 1B of FIG. 1A, while FIG. 1Cis an enlarged view of the area in the circle 1C of FIG. 1B.

[0067] As illustrated, the semiconductor device 215 is provided with asilicon substrate 201 (semiconductor substrate). One surface 201 a ofthis silicon substrate 201 is formed with a semiconductor elementformation layer 202 in which a transistor or other electronic element isbuilt. Further, the semiconductor element formation layer 202 has anelectrode pad 211 provided on it. While not shown, the electrode pad 211is electrically connected with an element in the semiconductor elementformation layer 202. The electrode pad 211 and silicon substrate 201have the element formation layer 202 interposed between them. Referencenumeral 204 indicates a passivation layer provided to protect thesemiconductor element formation layer 202. The layer is for examplecomprised of SiO₂.

[0068] Reference numeral 212 indicates a through hole passing throughthe electrode pad 211 and silicon substrate 201. An SiO₂ film 209(insulating film) is formed on its inner walls. The SiO₂ film 209 isalso formed on the other surface 201 b of the silicon substrate 201, onthe electrode pad 211 and on the extension 211X of the electrode pad211.

[0069] The SiO₂ film 209 on the extension 211X of the electrode pad 211is provided with a via hole 209 a. The electrode pad 211 and aninterconnection pattern 214 on the SiO₂ film are electrically connectedthrough this via hole 209 a.

[0070] Referring to FIG. 1B, the through hole 212 is defined by thefirst opening 208 and the second opening 201 c. Among these, the firstopening 208 is the portion passing through the electrode pad 211, whilethe second opening 201 c is the portion passing through the siliconsubstrate 201.

[0071] In the present invention, the diameter R1 of the first opening208 is made larger than the diameter R2 of the second opening 201 c.Specifically, R1 is about 50 to 70 μm, while R2 is made smaller than R1or about 25 to 50 μm. What is important is that R1>R2. The presentinvention is not limited to the above numerical values.

[0072] According to this structure, compared with the case where thediameters R1 and R2 are the same, it is possible to extend the distanceD1 (FIG. 1C) between the near open ends 208 a and 201 d of the firstopening 208 and second opening 201 c. Therefore, it is possible tosecure a sufficient insulation between the electrode pad 211 and siliconsubstrate 201 at the side walls of the through hole 212.

[0073] In the illustrated example, the second opening 201 c is formedtapered, but as explained later, this is due to the formation of thesecond opening 201 c by a laser beam. The shape is not limited to atapered one. For example, the advantages of the present invention can beobtained even if forming the second opening 201 c straight in shape.

[0074] Further, in the illustrated example, the through hole 212 ishollow, but as shown in FIG. 7, it is also possible to fill the throughhole 212 with a conductor 217 electrically connected with theinterconnection pattern 214. As the conductor 217 in this case, there isfor example copper.

[0075] On the other hand, if taking note of the interconnection pattern214 shown in FIG. 1A, this is formed over the SiO₂ film 209 and extendsto the other surface 201 b of the silicon substrate 201 through thethrough hole 212. The interconnection pattern 214 functions toelectrically connect the electrode pad 211 to the other surface 201 bthrough the via hole 209 a and through hole 212.

[0076] Predetermined locations of the interconnection pattern 214 leadout in this way are provided with solder bumps 210 functioning asexternal connection terminals. The external connection terminals,however, are not limited to the solder bumps 210. Stud bumps or otherknown external connection terminals may also be used.

[0077] By causing reflow of the solder bumps 210 in the state with thesolder bumps 210 abutting against terminal pads of the motherboard (notshown), the semiconductor device 215 is electrically and mechanicallyconnected on the motherboard.

[0078] The semiconductor device 215 may be used alone in this way or maybe used stacked as explained above.

[0079]FIG. 2 is a plan view of the semiconductor device 215 seen fromthe A side of FIG. 1A.

[0080] The interconnection pattern 214 formed on the surface 201 a isprovided with a terminal part 214 a. This terminal part 214 a isprovided to electrically lead out the electrode pad 211 to the surface201 a of the silicon substrate 201. When stacking a plurality ofsemiconductor devices 215 vertically, it is the portion where a solderbump 210 provided by the top semiconductor device 215 is bonded. Whenthere is no need for stacking, however, there is no need to provide theterminal part 214 a.

[0081] A sectional view of semiconductor devices 215 stacked in this wayis shown in FIG. 3. As shown in FIG. 3, the interconnection patterns 214of the facing surfaces of each top and bottom semiconductor device 215are electrically connected through the solder bumps 210. This structureis a three-dimensional mounting structure obtained by stacking aplurality of the semiconductor devices. The planar size of eachsemiconductor device 215 is smaller than in the related art, so in thisthree-dimensional structure, it is possible to keep down the lateralspread as compared with the related art. This contributes to the higherdensity and smaller size of semiconductor packages as sought in recentyears.

[0082] Note that when filling the through holes 212 with a conductor 217as shown in FIG. 7, the conductors 217 a of the portions exposed fromthe openings 212 a of the through holes 212 can be used instead of theterminal parts 214 a, so the terminal parts 214 a and theinterconnection patterns 214 at the portions where solder bumps 210 areprovided are unnecessary and the semiconductor devices 215 can be easilystacked. A sectional view of the semiconductor devices 215 in the caseof stacking in this way is given in FIG. 8.

[0083] The method of production of the above semiconductor device 215will be explained next with reference to FIGS. 4A to 4Q. FIGS. 4A to 4Qare sectional views of the semiconductor device in different steps ofproduction.

[0084] First, as shown in FIG. 4A, a silicon substrate 201(semiconductor substrate) is prepared. This silicon substrate 201 is asubstrate (wafer) for obtaining a large number of semiconductor devices.

[0085] Next, as shown in FIG. 4B, a transistor or other electronicelement is formed on one surface 201 a of the silicon substrate 201. Inthe figure, reference numeral 202 shows a semiconductor elementformation layer where the semiconductor element is formed.

[0086] Next, as shown in FIG. 4C, a film (not shown) comprised ofaluminum (first metal) is formed on the semiconductor element formationlayer 202 and this film patterned to form the bottom electrode pad 203.The thickness of the bottom electrode pad 203 is about 1 μm. Note thatinstead of aluminum, it is also possible to form the bottom electrodepad 203 by copper.

[0087] Since the bottom electrode pad 203 and the silicon substrate 201have the semiconductor element formation layer 202 interposed betweenthem, the bottom electrode pad 203 is positioned above the siliconsubstrate 201 without contacting the silicon substrate 201. Further,while not particularly shown, the bottom electrode pad 203 is formed soas to be electrically connected with an interconnection layer in thesemiconductor element formation layer 202.

[0088] Next, as shown in FIG. 4D, the bottom electrode pad 203 and thesemiconductor element formation layer 202 have formed on them apassivation layer 204 comprised of SiO₂ etc. Next, this passivationlayer 204 is patterned to form an opening 204 a where the bottomelectrode pad 203 is exposed.

[0089] Note that a product in the state shown in FIG. 4D can be obtainedfrom the semiconductor manufacturer. As shown in FIG. 4D, thesemiconductor substrate 201 formed with the bottom electrode pad 203 orsemiconductor element formation layer 202 and the passivation layer 204etc. is a general substrate usually produced by semiconductormanufacturers. The bottom electrode pad 203 is originally used as anelectrode pad for wire bonding or bonding of external connectionterminals (bumps etc.) (main electrode pad 110 in the example of therelated art).

[0090] Next, as shown in FIG. 4E, a power feed layer 205 a comprised ofCr (chrome) is formed on the passivation layer 204 and the exposedsurface of the bottom electrode pad 203. The power feed layer 205 a isformed by for example sputtering.

[0091] Next, as shown in FIG. 4F, a first photoresist 206 is coated onthe power feed layer 205 a. Suitably thereafter, the first photoresist206 is exposed and developed to form the first resist opening 206 asuperposed with the opening 204 a of the passivation layer 204.

[0092] Next, as shown in FIG. 4G, current is supplied to the power feedlayer 205 a in the state with the power feed layer 205 a exposed in thefirst resist opening 206 a immersed in a plating solution (not shown) soas to form the electroplated copper layer 205 b.

[0093] Next, as shown in FIG. 4H, the first photoresist 206 is removed,then the power feed layer 205 a which had been formed under the firstphotoresist 206 is selectively etched to remove it. By the steps up tohere, the top electrode pad 205 comprised of the power feed layer 205 aand the electroplated copper layer 205 b is completed. The thickness ofthe top electrode pad 205 is about 1 to 25 μm.

[0094] Further, in the present embodiment, the bottom electrode pad 203and the top electrode pad 205 form the electrode pad 211. Part of thetop electrode pad 205 extends leftwards in FIG. 4H to form an extension211X of the electrode pad 211.

[0095] Next, as shown in FIG. 4I, a second photoresist 207 is formed onthe passivation layer 204 and the exposed surface of the electrode pad211. Further, the photoresist 207 is exposed and developed to form asecond opening 207 a exposing the electrode pad 211.

[0096] Next, as shown in FIG. 4J, the photoresist 207 is used as anetching mask to pattern the electrode pad 211 and form a first opening208 in the electrode pad 211. The etching in this case is for examplechemical etching or plasma etching. Note that the diameter RI of thefirst opening is about 50 to 70 μm, but should be suitably set inaccordance with the diameter of the electrode pad 211.

[0097] Next, as shown in FIG. 4K, the other surface 201 b of the siliconsubstrate 201 is polished to reduce the thickness of the siliconsubstrate 201 to about 50 to 150 μm. By this step, the advantage isobtained that the later completed semiconductor device becomes thin, butwhen the semiconductor device does not have to be made thin, this stepmay be omitted.

[0098] Next, as shown in FIG. 4L, a laser beam having a smaller diameterthan the diameter R1 of the first opening 208 is fired through the firstopening 208. As an example of the laser, there is a UV laser, YAG laser,or excimer laser. The portion struck by the laser beam vaporizes,whereby a second opening 201 c is formed in the silicon substrate 201.The diameter R2 of this second opening 201 c is about 25 to 50 μm.Further, the through hole 212 is defined by the first opening 208 andthe second opening 201 c.

[0099] By firing a laser beam of a diameter smaller than the diameter R1after forming the first opening 208, the laser beam is prevented fromcontacting the first opening 208 and vaporizing the material of theelectrode pad 211 (aluminum or copper), so the danger of vaporizedmaterial depositing on the side walls of the through hole 212 andelectrically connecting the silicon substrate 201 and electrode pad 211is reduced.

[0100] In addition, a structure where the diameter R1 of the firstopening 208 is larger than the diameter R2 of the second opening 201 cis obtained. As explained above, this structure has the advantage thatthe insulation between the electrode pad 211 and the silicon substrate201 at the side walls of the through hole 212 can be sufficientlysecured.

[0101] Further, since the silicon substrate 201 is reduced in thicknessat the step of FIG. 4K before forming the second opening 201 c, it ispossible to form the second opening 201 c by firing the laser beam for ashort time, so heat damage to the silicon substrate 201 arising due tothe laser beam can be reduced.

[0102] Further, since the depth of working by the laser beam becomesshallow, the amount of the silicon vaporized by the laser beam isreduced and the amount of the silicon which is vaporized and deposits inthe through hole 212 is reduced. Due to this, it is possible to cleanlyform the through hole 212.

[0103] Note that when heat damage or deposition of silicon in thethrough hole 212 is not an issue, the step of FIG. 4K (step of reducingthe thickness of the silicon substrate 201) may be omitted.

[0104] Further, while the second opening 201 c illustrated is tapered,this is because a laser beam focused to a point by a focusing lens (notshown) instead of a laser beam of parallel light is used. The secondopening 201 c does not have to be tapered in shape. For example, theadvantages of the present invention can be obtained even if the secondopening 201 c is formed straight in shape.

[0105] Further, as shown in FIG. 4L, the second opening 201 c may beformed by firing the laser beam from the other surface 201 b of thesilicon substrate 201 instead of firing the laser beam through the firstopening 208. Even when doing this, it is similarly possible to preventsilicon vaporized by the laser from depositing on the electrode pad 211.

[0106] Still further, the step shown in FIG. 6 may be performed betweenthe steps of FIG. 4K and FIG. 4L. In this step, an SiO₂ film or otherprotective film 216 is formed by chemical vapor deposition (CVD) on thepassivation layer 204, on the electrode pad 211 including the extension211X, on the side walls of the first opening 208, and on thesemiconductor element formation layer 202 exposed from the first opening208. At the time of laser processing of FIG. 4L, if debris or burrsoccur due to the laser beam, these are cleaned away (plasma cleaning orchemical washing). If the protective film 216 is formed as explainedabove, it is possible to prevent damage to the electrode pad 211 orpassivation layer 204 at the time of cleaning.

[0107] After forming the through hole 212, the step shown in FIG. 4M isperformed. In this step, an SiO₂ film 209 (insulating film) is formed atleast on the other surface 201 b of the semiconductor substrate 201, onthe inner walls of the through hole 212, and on the electrode pad 211including the extension 211X. The SiO₂ film 209 is formed by for examplechemical vapor deposition (CVD).

[0108] Note that to form the SiO₂ film 209 on the two main surfaces ofthe semiconductor substrate 201 as illustrated, for example, first, anSiO₂ film 209 may be formed on only the surface 201 a of thesemiconductor substrate 201 and the side walls of the through hole 212,then the SiO₂ film 209 formed on the other surface 201 b.

[0109] Next, as shown in FIG. 4N, the SiO₂ film 209 is patterned to formthe via hole 209 a exposing part of the extension 211X of the electrodepad 211.

[0110] As the method of forming the via hole 209 a, for example, it ispossible to form a resist (not shown) having an opening corresponding tothat shape on the SiO₂ film 209 and selectively etch the SiO₂ filmthrough that opening. The etching technique used at that time is forexample chemical etching or plasma etching.

[0111] As another method, it is possible to fire a laser beam at theSiO₂ film 209 at the location where the via hole 209 a should be formedto cause that portion to vaporize and thereby form the via hole 209 a.For example, it is possible to place a light-shielding mask (not shown)having a window of a shape corresponding to the via hole 209 a againstthe laser beam and open the via hole 209 a by the laser beam passingthrough that window.

[0112] After forming the via hole 209 a, the step shown in FIG. 4O isperformed. In this step, the conductive film 213 is formed on the SiO₂film 209 and in the via hole 209 a. The thickness of the conductive film213 is about 1 to 20 μm.

[0113] The conductive film 213, as shown in FIG. 4P, is comprised of aCr (chrome) film 213 a formed by sputtering, a copper film 213 b formedover it also by sputtering, and an electroplated copper film 213 cformed using the Cr (chrome) film 213 a and copper film 213 b as powerfeed layers. The structure of the conductive film 213, however, is notlimited to this. For example, it is also possible to form an aluminumfilm by sputtering and use the aluminum film as a conductive film 213.Alternatively, it is possible to form a Cr (chrome) film by sputtering,then form a Cu (copper), Ni (nickel), Au (gold), or other film byelecroless plating or electroplating on the Cr (chrome) film for use asthe conductive film 213.

[0114] Note that in the illustrated example, the through hole 212 ishollow, but the present invention is not limited to this. For example,it is also possible to fill the inside of the through hole 212 by aconductor 217 comprised of copper by thickly applying the electroplatedcopper film 213 c as shown by the enlarged sectional view of FIG. 7.

[0115] The method of filling is not limited to the above method. Forexample, it is also possible to form the conductive film 213 to athickness of about 1 to 20 μm, then form a plating resist layer providedwith an opening exposing only the side walls of the through hole 212 andelectrolytically copper plate the side walls so as to fill the throughhole 212 with copper. In this method, the conductive film 213 does notbecome thick, so it is possible to finely pattern the conductive layer213 in a later step. Note that whatever the method, the conductor 217should electrically connect with the conductive film 213.

[0116] Next, an explanation will be given of a case of not filling aconductor 217, but the same steps may be used even when filling theconductor 217.

[0117] After forming the conductive layer 213, as shown in FIG. 4Q, theconductive film 213 is patterned to form interconnection patterns 214.The interconnection patterns 214 are formed on the two main surfaces 201a and 201 b of the silicon substrate 201. The interconnection patterns214 of the two main surfaces 201 a and 201 b are electrically connectedthrough the through hole 212.

[0118] Next, as shown in FIG. 1A, predetermined locations of theinterconnection pattern 214 on the other surface 201 b of the siliconsubstrate 201 are provided with solder bumps 210 serving as externalconnection terminals, then the substrate is diced, whereby semiconductordevices as shown in FIG. 1A are completed.

[0119] The completed semiconductor devices 215 may be mounted alone on amotherboard (not shown) or may be stacked.

[0120] When stacking them, as explained in FIG. 2, terminal parts 214 aare provided at the interconnection patterns 214. As shown in FIG. 5, aplurality of the completed semiconductor devices 215 are prepared.

[0121] Next, as shown in FIG. 3, the solder bumps 210 are made to reflowin the state with the solder bumps 210 abutting against the terminalparts 214 a of the bottom semiconductor devices 215. After reflow, thetemperature of the solder bumps 215 falls, whereby a semiconductormodule of a three-dimensional mounting structure comprised of a largenumber of stacked semiconductor devices 215 is completed.

[0122] Further, when filling the through holes 212 with the conductor217, as shown in FIG. 8, the conductors 217 a of the portions exposedfrom the openings 212 a of the through holes 212 function as the aboveterminal parts 214 a, so the terminal parts 214 a and theinterconnection patterns 214 of the locations of provision of the solderbumps 210 are unnecessary.

[0123] Summarizing the effects of the invention, as explained above, thediameter of the through hole is made larger at the portion passingthrough the electrode pad than the portion passing through thesemiconductor substrate so that insulation between the electrode pad andthe semiconductor substrate can be sufficiently secured at the sidewalls of the through hole.

[0124] While the invention has been described with reference to specificembodiments chosen for purpose of illustration, it should be apparentthat numerous modifications could be made thereto by those skilled inthe art without departing from the basic concept and scope of theinvention.

[0125] The present disclosure relates to subject matter contained inJapanese Patent Application No. 2001-180893, filed on Jun. 14, 2001, thedisclosure of which is expressly incorporated herein by reference in itsentirety.

What we claim is:
 1. A semiconductor device comprised of: asemiconductor substrate; an electronic element formed on one surface ofsaid semiconductor substrate; an electrode pad having an extension,formed on said one surface and electrically connected with saidelectronic element; a through hole passing through said electrode padand said semiconductor substrate; an insulating film formed on at leastthe other surface of said semiconductor substrate, an inner wall of saidthrough hole, and said electrode pad including said extension; a viahole provided in said insulating film on said extension of saidelectrode pad; an interconnection pattern electrically leading out saidelectrode pad to the other surface of said semiconductor substratethrough said through hole and said via hole; and said through holehaving a diameter larger at a portion passing through said electrode padthan a portion passing through said semiconductor substrate.
 2. Asemiconductor device as set forth in claim 1, wherein saidinterconnection pattern electrically leads out said electrode pad to theone surface of said semiconductor substrate as well.
 3. A semiconductormodule comprised of a plurality of semiconductor devices as set forth inclaim 2 stacked together and having interconnection patterns of facingsurfaces of each bottom semiconductor device and top semiconductordevice electrically connected through external connection terminals. 4.A semiconductor device as set forth in claim 1, wherein said throughhole is filled by a conductor electrically connected with saidinterconnection pattern.
 5. A semiconductor module comprised of aplurality of semiconductor devices as set forth in claim 4 stackedtogether and having conductors filled in corresponding through holes ofeach bottom semiconductor device and top semiconductor deviceelectrically connected through external connection terminals.
 6. Amethod of production of a semiconductor device comprising the steps of:forming an electronic element on one surface of a semiconductorsubstrate; forming an electrode pad having an extension and electricallyconnected with said electronic element on said one surface of thesemiconductor substrate; forming a first opening in said electrode padby patterning; forming a second opening in said semiconductor substrateincluding said electronic element by firing through said first opening alaser beam of a smaller diameter than the diameter of said firstopening, thereby defining a through hole by said first opening and saidsecond opening; forming an insulating film on at least the other surfaceof said semiconductor substrate, an inner wall of said through hole, andsaid electrode pad including said extension; forming a via hole exposingpart of said extension of said electrode pad by patterning saidinsulating film; forming a conductive film on said insulating film andin said via hole; and forming an interconnection pattern electricallyleading said electrode pad to the other surface of said semiconductorsubstrate through said through hole and said via hole by patterning saidconductive film.
 7. A method of production of a semiconductor device asset forth in claim 6, wherein the step of forming the first opening andthe step of forming the second opening include between them a step ofpolishing the other surface of the semiconductor substrate to reduce thethickness of the semiconductor substrate.
 8. A method of production of asemiconductor device as set forth in claim 6, wherein the step offorming the via hole is performed by opening said insulating film by alaser beam.
 9. A method of production of a semiconductor device as setforth in claim 6, wherein by the step of forming said interconnectionpattern, said interconnection pattern is formed so that said electrodepad is electrically led out to the one surface of said semiconductorsubstrate as well.
 10. A method of production of a semiconductor modulecomprising the steps of: preparing a plurality of semiconductor devicesproduced by the method set forth in claim 9 and stacking saidsemiconductor devices in a plurality of layers by electricallyconnecting the interconnection patterns of said semiconductor devicethrough external connection terminals.
 11. A method of production of asemiconductor device as set forth in claim 6, including a step offilling said through hole by a conductor electrically connected to saidconductive film after the step of forming said conductive film.
 12. Amethod of production of a semiconductor module comprising the steps of:preparing a plurality of semiconductor devices produced by the methodset forth in claim 11 and stacking said semiconductor devices in aplurality of layers by electrically connecting the conductors exposedfrom openings of corresponding through holes of said plurality ofsemiconductor device through external connection terminals.